View IXDI430MCI_7961876.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

first release copyright ? ixys corporation 2005 ordering information general description the ixdn430/ixdi430/ixdd430/ixds430 are high speed high current gate drivers specifically designed to drive mosfets and igbts to their minimum switching time and maximum practical frequency limits. the ixd_430 can source and sink 30a of peak current while producing voltage rise and fall times of less than 30ns. the input of the drivers are compatible with ttl or cmos and are fully immune to latch up over the entire operating range. designed with small internal delays, cross conduction/current shoot-through is virtually eliminated in all configurations. their features and wide safety margin in operating voltage and power make the drivers unmatched in performance and value. the ixd_430 incorporates a unique ability to disable the output under fault conditions. the standard undervoltage lockout voltages are 11.75v for the ixd_430 parts and 8.5v for the ixd_430m parts. ulvo can be set to either level in the ixds430 with the unsel input line. when a logical low is forced into the enable inputs, both final output stage mosfets (nmos and pmos) are turned off. as a result, the output of the ixdd430 enters a tristate mode and enables a soft turn-off of the mosfet when a short circuit is detected. this helps prevent damage that could occur to the mosfet if it were to be switched off abruptly due to a dv/dt over-voltage transient. the ixdn430 is configured as a noninverting gate driver, and the ixdi430 is an inverting gate driver. the ixds430 can be configured either as a noninverting or inverting driver. the ixd_430 are available in the standard 28-pin sioc (si-ct), 5-pin to-220 (ci), and in the to-263 (yi) surface mount packages. ct or 'cool tab' for the 28-pin soic package refers to the backside metal heatsink tab. features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected ? high peak output current: 30a peak ? wide operating range: 8.5v to 35v ? under voltage lockout protection ? ability to disable output under faults ? high capacitive load drive capability: 5600 pf in <25ns ? matched rise and fall times ? low propagation delay time ? low output impedance ? low supply current applications ? driving mosfets and igbts ? motor controls ? line drivers ? pulse generators ? local power on / off switch ? switch mode power supplies (smps) ? dc to dc converters ? pulse transformer driver ? limiting di/dt under short circuit ? class d switching amplifiers part number package type temp. range configuration undervoltage lock-out ixdd430yi ixdd430myi 5-pin to-263 11.75 v 8.5 v ixdd430ci ixdd430mci 5-pin to-220 -55c to +125 non inverting with enable 11.75 v 8.5 v ixdi430yi ixdi430myi 5-pin to-263 11.75 v 8.5 v ixdi430ci IXDI430MCI 5-pin to-220 -55c to +125 inverting 11.75 v 8.5 v ixdn430yi ixdn430myi 5-pin to-263 11.75 v 8.5 v ixdn430ci ixdn430mci 5-pin to-220 -55c to +125 non inverting 11.75 v 8.5 v ixds430si 28-pin soic -55c to +125 inverting / non inverting w ith enable and uvsel 11.75 v or 8.5 v 30 amp low-side ultrafast mosfet / igbt driver ixdn430 / ixdi430 / ixdd430 / ixds430 ds99045c(04/04)
2 ixdn430 / ixdi430 / ixdd430 / ixds430 figure 1c - ixdi430 (inverting) diagram figure 1a - ixdd430 (non inverting with enable) diagram figure 1b - ixdn430 (non-inverting) diagram figure 1d - ixds430 (inverting and non inverting with enable) diagram notes: 1. out p and out n are connected together in the 5 lead to-220 and to-263 packages; 2. ixds430: undervoltage lock-out is set by uvsel. uvsel = vcc, uvlo = 8.5v, uvsel = open, uvlo = 11.75v. inv 400k 400k 1k gnd gnd vcc vcc out n out p in en uvsel uvcc 1k out gnd gnd vcc vcc in en 400k uvcc out vcc 1k gnd gnd vcc in uvcc out vcc 1k gnd gnd vcc in uvcc
3 ixdn430 / ixdi430 / ixdd430 / ixds430 unless otherwise noted, t a = 25 o c, 8.5v v cc 35v . all voltage measurements with respect to gnd. ixdd430 configured as described in test conditions . electrical characteristics symbol parameter test conditions min typ max units v ih high input voltage 0v v in v cc, 8.5v v in 18v 3.5 v v il low input voltage 0v v in v cc, 8.5v v in 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high v cc = 18v 0.3 0.4 ? r ol output resistance @ o utput low v cc = 18v 0.2 0.3 ? i peak peak output current v cc = 18v 30 a i dc continuous output current limited by package power dissipation 8 a v en enable voltage range ixdd430 only - 0.3 vcc + 0.3 v v enh high en input voltage ixdd430 only 2/3 vcc v v enl low en input voltage ixdd430 only 1/3 vcc v r en en input resistance ixds430 only 400 kohm v inv inv voltage range ixds430 only - 0.3 vcc + 0.3 v v invh high inv input voltage ixds430 only 2/3 vcc v v invl low inv input voltage ixds430 only 1/3 vcc v r in v inv input resistance ixds430 only 400 kohm t r rise tim e c l =5600pf vcc=18v 18 20 ns t f f all tim e c l =5600pf vcc=18v 16 18 ns t ondly on-time propagation delay c l =5600pf vcc=18v 41 45 ns t offdly off-time propagation delay c l =5600pf vcc=18v 35 39 ns t enoh enable to output high delay time ixdd430 only, vcc=18v 47 ns t dold disable to output low delay time ixdd430 only, vcc=18v 120 ns v cc power supply voltage 8.5 18 35 v i cc power supply current v in = 3.5v v in = 0v v in = +v cc 1 0 3 10 10 ma a a u vlo ixd _430m ; ixd s430: ixd _430; ixd s 430: uvsel = v cc (m o sfet) uvsel = open (igbt) 7.5 10.5 8.5 11.75 9.5 13.0 v v absolute maximum ratings (note 1) paramete r v alue supply voltage 40 v all other pins -0.3 v to v cc + 0.3 v power dissipation, t ambient 25 o c to220 (ci), to263 (yi) 2w derating factors (to ambient) to220 (ci), to263 (yi) 0.016w/ o c storage temperature -65 o c to 150 o c lead temperature (10 sec) 300 o c operating ratings param eter v alue maximum junction temperature 150 o c operating temperature range -55 o c to 125 o c thermal impedance to220 (ci), to263 (yi) jc (junction to case) 0.95 o c/w ja (junction to ambient) 62.5 o c/w thermal impedance 28 pin soic with heat slug (si) jc (junction to case) 3 o c/w specifications subject to change without notice note 1: operating the device beyond parameters with listed ?absolute maximum ratings? may cause permanent damage to the device. typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. the guaranteed specifications apply only for the test conditions listed. exposure to absolute maximum rated conditions for extended periods may affect device reliability.
4 ixdn430 / ixdi430 / ixdd430 / ixds430 symbol paramete r test conditions min typ max units v ih high input voltage 8.5 vcc 18v 3.5 v v il low input voltage 8.5 vcc 18v 1.1 v v in input voltage range -5 v cc + 0.3 v r oh output resistance @ output high v cc = 18v 0.46 ? r ol output resistance @ output low v cc = 18v 0.4 ? t r rise time c l =5600pf vcc=18v 20 ns t f fall time c l =5600pf vcc=18v 18 ns t ondly on-time propagation delay c l =5600pf vcc=18v 58 ns t offdly off-time propagation delay c l =5600pf vcc=18v 51 ns v cc power supply voltage 8.5 18 35 v electrical characteristics unless otherwise noted, temperature over -55 o c to +125 o c, 4.5 v cc 35v . all voltage measurements with respect to gnd. ixdd430 configured as described in test conditions . note: mounting tabs, solder tabs, or heat sink metalization on all packages are connected to ground. 5-lead to-220 outline (ixd_430ci, ixd_430mci) 28-pin soic outline (ixd_430si) 5-lead to-263 outline (ixd_430yi, ixd_430myi)
5 ixdn430 / ixdi430 / ixdd430 / ixds430 pin description symbol function description vcc supply voltage positive power-supply voltage input. this pin provides power to the entire chip. the range for this voltage is from 8.5v to 35v. in input input signal-ttl or cmos compatible. en * enable the system enable pin. this pin, when driven low, disables the chip, forcing high impedance state to the output (ixdd430 only). inv invert forcing inv low causes the ixds430 to become non-inverted, while forcing inv high causes the ixds430 to become inverted. out p out n output respective p and n driver outputs. for application purposes this pin is connected, through a resistor, to gate of a mosfet/igbt. the p and n output pins are connected together in the to-263 and to-220 packages. gnd ground the system ground pin. internally connected to all circuitry, this pin provides ground reference for the entire chip. this pin should be connected to a low noise analog ground plane for optimum performance. uvsel select under voltage level with uvsel connected to vcc, ixds430 outputs go low at vcc < 8.5v; with uvsel open, under voltage level is set at vcc < 12.5v figure 2 - characteristics test diagram * this pin is used only on the ixdd430, and is n/c (not connected) on the ixdi430 and ixdn430. caution: these devices are sensitive to electrostatic discharge; follow proper esd procedures when handling and assembling this component. to220 (ci) to263 (yi) vc c out gnd in e n * 1 2 3 4 5 pin configurations (si-ct) 28 pin soic vcc 4 vcc 3 vcc 2 vcc 1 25 vcc 26 vcc 27 vcc 28 vcc 18 gnd gnd 11 16 gnd 17 gnd 15 gnd gnd 13 gnd 12 22 out p 23 out p 24 out p 19 out n 20 out n 21 out n gnd 14 n/c 7 n/c 5 uvsel 6 in 8 en 9 inv 10 + vin - vcc en in gnd out vcc + ixdd430 c load - c bypass/ .. filter
6 ixdn430 / ixdi430 / ixdd430 / ixds430 rise and fall times vs. temperature c l = 5600 pf, vcc = 18v 0 5 10 15 20 25 -60 -10 40 90 140 190 temperature (c) time (ns) t r t f output rise times vs. load capacitance 5 10 15 20 25 30 1000 3000 5000 7000 9000 11000 13000 15000 load capacitance (pf) rise time (ns) 13v 18v 35v output fall times vs. load capacitance 0 5 10 15 20 25 30 1000 3000 5000 7000 9000 11000 13000 15000 load capacitance (pf) fall time (ns) 13v 18v 35v rise times vs. supply voltage 0 5 10 15 20 25 30 35 10 15 20 25 30 35 supply voltage (v) rise time (ns) 1000 pf 5600 pf 10000 pf 15000 pf fall times vs. supply voltage 0 5 10 15 20 25 30 10 15 20 25 30 35 supply voltage (v) fall time (ns) 1000 pf 5600 pf 10000 pf 15000 pf typical performance characteristics fig. 3 fig. 4 fig. 5 fig. 6 fig. 7 fig. 8 max / min input vs. temperature cl = 5600pf, vcc = 18v 0 0.5 1 1.5 2 2.5 3 3.5 4 -60 -10 40 90 140 190 temperature (c) max / min input voltage min input high max input low
7 ixdn430 / ixdi430 / ixdd430 / ixds430 supply current vs. frequency vcc = 25v 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1000 pf 5600 pf 10000 pf 15000 p f supply current vs. load capacitance vcc = 25v 0 50 100 150 200 250 300 350 400 1000 10000 100000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. frequency vcc = 18v 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1000 p f 5600 p f 10000 p f 15000 p f supply current vs. load capacitance vcc = 18v 0 50 100 150 200 250 300 1000 10000 100000 load capacitance (pf) supply current (ma) 2 mhz 1 mhz 500 khz 100 kh z 50 khz 10 khz supply current vs. load capacitance vcc = 13v 0 50 100 150 200 250 300 1000 10000 100000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. frequency vcc = 13v 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1000 p f 5600 p f 10000 p f 15000 p f fig. 10 fig. 11 fig. 12 fig. 14 fig. 9 fig. 13
8 ixdn430 / ixdi430 / ixdd430 / ixds430 supply current vs. load capacitance vcc = 35v 0 50 100 150 200 250 300 350 400 1000 10000 100000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 500 khz 1 mhz supply current vs. frequency vcc = 35v 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1000 pf 5600 p f 10000 p f 15000 p f fig. 16 fig. 17 fig. 18 fig. 19 fig. 20 fig. 15 quiescent supply current vs. temperature vcc = 18v, vin = 15v@1khz, c l = 5600pf 0 0.1 0.2 0.3 0.4 0.5 0.6 -60 -10 40 90 140 190 temperature (c) quiescent vcc input current (ma) propagation delay times vs. temperature c l = 5600pf, vcc = 18v 0 10 20 30 40 50 60 70 -60 -10 40 90 140 190 temperature (c) time (ns) t ondly t offdly propagation delay vs. supply voltage c l = 5600 pf vin = 15v@1khz 0 5 10 15 20 25 30 35 40 45 50 10 15 20 25 30 35 supply voltage (v) propagation delay (ns) t ondly t offdly propagation delay vs. input voltage c l = 5600 pf vcc = 18v 0 5 10 15 20 25 30 35 40 45 50 5 10152025 input voltage (v) propagation delay (ns) t ondly t offdly
9 ixdn430 / ixdi430 / ixdd430 / ixds430 n channel output current vs. temperature vcc = 18v 0 5 10 15 20 25 30 35 40 45 -60 -10 40 90 140 190 temperature (c) n channel output current (a) p channel output current vs. vcc -80 -70 -60 -50 -40 -30 -20 -10 0 10 15 20 25 30 35 40 vcc (v) p channel output current (a) high state output resistance vs. supply voltage 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 10 15 20 25 30 35 40 supply voltage (v) high state output resistance (ohms) p channel output current vs. temperature vcc = 18v 0 5 10 15 20 25 30 35 40 -60 -10 40 90 140 190 temperature (c) p channel output current (a) fig. 21 fig. 22 fig. 23 fig. 24 n channel output current vs. vcc 0 10 20 30 40 50 60 70 10 15 20 25 30 35 40 vcc (v) n channel output current (a) fig. 25 fig. 26 low state output resistance vs. supply voltage 0 0.05 0.1 0.15 0.2 0.25 10 15 20 25 30 35 40 supply voltage (v) low state output resistance (ohms)
10 ixdn430 / ixdi430 / ixdd430 / ixds430 figure 28 - ixdd430 application test diagram figure 27 - typical circuit to decrease di/dt during turn-off 10uh ld 0.1ohm rd rs 20nh ls 1ohm rg 10kohm r+ vmo580-02f hi g h _ power 5kohm rcomp 100pf c+ + - v+ v- comp lm339 1600ohm rsh ccomp 1pf vcc vcca in en gnd out ixdd430 + - vin + - vcc + - ref + - vb cd4001a nor2 1mohm ros not2 cd4049a cd4011a nand cd4049a not1 cd4001a nor1 cd4049a not3 low _ power 2n7002/plp 1pf cos 0 s r en q one shot circuit sr flip-flop gnd
11 ixdn430 / ixdi430 / ixdd430 / ixds430 short circuit di/dt limit a short circuit in a high-power mosfet module such as the vm0580-02f, (580a, 200v), as shown in figure 27, can cause the current through the module to flow in excess of 1500a for 10 s or more prior to self-destruction due to thermal runaway. for this reason, some protection circuitry is needed to turn off the mosfet module. however, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to ldi/dt, (where l represents total inductance in series with drain). if these voltage transients exceed the mosfet's voltage rating, this can cause an avalanche break- down. the ixdd430 has the unique capability to softly switch off the high-power mosfet module, significantly reducing these ldi/dt transients. thus, the ixdd430 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. the ixdd430 is designed to not only provide 30a under normal conditions, but also to allow it's output to go into a high impedance state. this permits the ixdd430 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control d vgs /dt gate turnoff. this circuit is shown in figure 28. referring to figure 28, the protection circuitry should include a comparator, whose positive input is connected to the source of the vm0580-02. a low pass filter should be added to the input of the comparator to eliminate any glitches in voltage caused by the inductance of the wire connecting the source resistor to ground. (those glitches might cause false triggering of the comparator). the comparator's output should be connected to a srff( set reset flip flop). the flip-flop controls both the enable signal, and the low power mosfet gate. please note that cmos 4000-series devices operate with a v cc range from 3 to 15 vdc, (with 18 vdc being the maximum allowable limit). a low power mosfet, such as the 2n7000, in series with a resistor, will enable the vmo580-02f gate voltage to drop gradually. the resistor should be chosen so that the rc time constant will be 100us, where "c" is the miller capacitance of the vmo580-02f. for resuming normal operation, a reset signal is needed at the srff's input to enable the ixdd430 again. this reset can be generated by connecting a one shot circuit between the ixdd430 input signal and the srff restart input. the one shot will create a pulse on the rise of the ixdd430 input, and this pulse will reset the srff outputs to normal operation. when a short circuit occurs, the voltage drop across the low- value, current-sensing resistor, (rs=0.005 ohm), connected between the mosfet source and ground, increases. this triggers the comparator at a preset level. the srff drives a low input into the enable pin disabling the ixdd430 output. the srff also turns on the low power mosfet, (2n7000). in this way, the high-power mosfet module is softly turned off by the ixdd430, preventing its destruction. applications information supply bypassing and grounding practices, output lead inductance when designing a circuit to drive a high speed mosfet utilizing the ixdd430/ixdi430/ixdn430, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. particular attention needs to be paid to supply bypassing , grounding , and minimizing the output lead inductance. say, for example, we are using the ixdd430 to charge a 15nf capacitive load from 0 to 25 volts in 25ns. using the formula: i= c ? v / ? t, where ? v=25v c=15nf & ? t=25ns we can determine that to charge 15nf to 25 volts in 25ns will take a constant current of 15a. (in reality, the charging current won?t be constant, and will peak somewhere around 30a). supply bypassing in order for our design to turn the load on properly, the ixdd430 must be able to draw this 5a of current from the power supply in the 25ns. this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected, low inductance, low resistance, high-pulse current-service capacitors). lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the ixdd430 to an absolute minimum. grounding in order for the design to turn the load off properly, the ixdd430 must be able to drain this 5a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixdd430 and it?s load. path #2 is between the ixdd430 and it?s power supply. path #3 is between the ixdd430 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. in addition, every effort should be made to keep these three ground paths distinctly separate. otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the ixdd430.
12 ixdn430 / ixdi430 / ixdd430 / ixds430 ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 www.ixys.com e-mail: sales@ixys.net output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and it?s load as short and wide as possible. if the driver must be placed farther than 2? from the load, then the output leads should be treated as transmission lines. in this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connect directly to the ground terminal of the load. a ttl high, v ttlhigh =>~2.4v, or a 5v cmos high, v 5vcmoshigh =~>3.5v, applied to the en input of the circuit in figure 29 will cause q1 to be biased off. this results in q1 collector being pulled up by r3 to v cc =15v, and provides a high voltage cmos logic high output. the high voltage cmos logical en output applied to the ixdd430 en input will enable it, allowing the gate driver to fully function as an 30 amp output driver. the total component cost of the circuit in figure 29 is less than $0.10 if purchased in quantities >1k pieces. it is recommended that the physical placement of the level translator circuit be placed close to the source of the ttl or cmos logic circuits to maximize noise rejection. figure 29 - ttl to high voltage cmos level translator ttl to high voltage cmos level translation (ixdd430 only) the enable (en) input to the ixdd430 is a high voltage cmos logic level input where the en input threshold is ? v cc , and may not be compatible with 5v cmos or ttl input levels. the ixdd430 en input was intentionally designed for enhanced noise immunity with the high voltage cmos logic levels. in a typical gate driver application, v cc =15v and the en input threshold at 7.5v, a 5v cmos logical high input applied to this typical ixdd430 application?s en input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. the note below is for optional adaptation of ttl or 5v cmos levels. a ttl or 5v cmos logic low, v ttllow =~<0.8v, input applied to the q1 emitter will drive it on. this causes the level translator output, the q1 collector output to settle to v cesatq1 + v ttllow =<~2v, which is sufficiently low to be correctly interpreted as a high voltage cmos logic low (<1/3v cc =5v for v cc =15v given in the ixdd430 data sheet.) the circuit in figure 29 alleviates this potential logic level misinterpretation by translating a ttl or 5v cmos logic input to high voltage cmos logic levels needed by the ixdd430 en input. from the figure, v cc is the gate driver power supply, typically set between 8v to 20v, and v dd is the logic power supply, typically between 3.3v to 5.5v. resistors r1 and r2 form a voltage divider network so that the q1 base is positioned at the midpoint of the expected ttl logic transition levels. q1 2n3904 r1 10k r2 10k r3 10k vdd en vcc (from gate driver power supply) power supply) 5v cmos or ttl input (from logic (to ixdd430 en input) cmos en output high voltage ds99045a(8/03)

▲Up To Search▲

Price & Availability of IXDI430MCI

	To Download IXDI430MCI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .